Commit 2c61f418 authored by Khoi Lam's avatar Khoi Lam 💬
Browse files

Lab 4, In Progress

parent 061ac0a7
......@@ -9,15 +9,15 @@ PC = Register()
# construct a memory segment for instruction memory
# load the contents from the 32-bit fetch_test hex file (big endian)
imem = readmemh('riscv_isa/programs/fetch_test.hex',
word_size = 4, byteorder = 'big')
# imem = readmemh('riscv_isa/programs/fetch_test.hex',
# word_size = 4, byteorder = 'big')
def display():
if pc_val == None:
return "PC: xxxxxxxx, IR: xxxxxxxx"
else:
return f"PC: {pc_val:08x}, IR: {instr.val:08x}, {instr}" # {instr} just returns the representation of the instruction that we overloaded with __str__
# run cpu
startup = True
# generate system clocks until we reach a stopping condition
# this is basically the run function from the last lab
......
# filename: fetch_decode.py
import itertools
import sys
from pydigital.memory import readmemh
from pydigital.register import Register
from riscv_isa import Instruction
from regfile import RegFile
# the PC register
PC = Register()
# construct a memory segment for instruction memory
# load the contents from the 32-bit fetch_test hex file (big endian)
# imem = readmemh('riscv_isa/programs/fetch_test.hex',
# word_size = 4, byteorder = 'big')
pc_val = PC.out()
def display(pc_val, instr):
if pc_val == None:
return "PC: xxxxxxxx, IR: xxxxxxxx"
else:
return f"PC: {pc_val:08x}, IR: {instr.val:08x}, {instr}" # {instr} just returns the representation of the instruction that we overloaded with __str__ in isa.py
# run cpu
def run_cpu():
startup = True
imem = readmemh('riscv_isa/programs/fetch_test.hex',
word_size = 4, byteorder = 'big')
#create the regfile
my_reg = RegFile()
# generate system clocks until we reach a stopping condition
# this is basically the run function from the last lab
for t in itertools.count(): # t represents clock
# sample inputs
pc_val = PC.out()
# access instruction memory
instr = Instruction(imem[pc_val], pc_val)
# RESET the PC register
if startup:
PC.reset(imem.begin_addr)
startup = False
print(f"{t:20d}:", display(pc_val, instr))
continue
# print one line at the end of the clock cycle
print(f"{t:20d}:", display(pc_val, instr))
# clock logic blocks, PC is the only clocked module!
# here the next pc value is always +4
PC.clock(4 + pc_val)
#display the register file
# check stopping conditions on NEXT instruction
if PC.out() > 0x1100:
print("STOP -- PC is large! Is something wrong?")
break
if imem[PC.out()] == 0:
print("Done -- end of program.")
break
my_reg.display()
if __name__ == "__main__":
if len(sys.argv) == 1:
program_file = "riscv_isa/programs/fetch_test.hex" #default instruction file
else:
program_file = sys.argv[1] #or choose another file
#construct a memory segment for the instruction memory
#load the contents from the 32-bit fetch_test hex file (big endian)
imem = readmemh(program_file, word_size = 4, byteorder = 'big')
#dmem = Memory(MemorySegment(0xE0000, count = 0x10000)) #for lab 5
sys.exit(run_cpu())
......@@ -19,7 +19,7 @@ class RegFile():
'''
return self.registers[rs]
def write(self, wa, wd, en):
def clock(self, wa, wd, en):
'''
wa: address to write to
wd: content to write to an address
......@@ -32,10 +32,7 @@ class RegFile():
return
else:
self.registers[wa] = wd
def display(self):
#Source: Prof. Marchiori
fmt_reg = lambda i: f"{self.registers[i]:09x}" if self.registers[i] != None else " xxxxxxx"
......@@ -49,5 +46,5 @@ if __name__ == "__main__":
myRegFile = RegFile()
registers = list(range(32))
for i in registers:
myRegFile.write(registers[i], wd+registers[i], en)
myRegFile.clock(registers[i], wd+registers[i], en)
myRegFile.display()
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