fixed 4

onestage_pt1.py

@@ -3,7 +3,7 @@ import itertools
 import sys
 from pydigital.memory import readmemh
 from pydigital.register import Register
-from pydigital.utils import sextend, twos_comp
+from pydigital.utils import twos_comp, twos_comp
 from riscv_isa import Instruction
 from riscv_isa import decoder
 from riscv_isa.isa import regNumToName
@@ -59,9 +59,9 @@ for t in itertools.count():
     rs1Val = None
     rs2Val = None
 
-    if instr.rs1 != "":
+    if instr.rs1 != None:
         rs1Val = RF.read(int(instr.rs1b, 2))
-    if instr.rs2 != "":
+    if instr.rs2 != None:
         rs2Val = RF.read(int(instr.rs2b, 2))
 
     if instr.name == "li":
@@ -75,9 +75,9 @@ for t in itertools.count():
     rf_wen = control[instr.name].rf_wen
     wb_sel = control[instr.name].wb_sel
 
-    op1Mux = make_mux(lambda: rs1Val, lambda: sextend(int(instr.binVal[0:20], 2), 20) << 12)
-    op2Mux = make_mux(lambda: rs2Val, lambda: sextenssd(int(instr.binVal[0:7] + instr.binVal[20:25], 2), 12), \
-        lambda: sextend(int(instr.binVal[0:12], 2), 12), pc_val)
+    op1Mux = make_mux(lambda: rs1Val, lambda: twos_comp(int(instr.binVal[0:20], 2), 20) << 12)
+    op2Mux = make_mux(lambda: rs2Val, lambda: twos_comp(int(instr.binVal[0:7] + instr.binVal[20:25], 2), 12), \
+        lambda: twos_comp(int(instr.binVal[0:12], 2), 12), pc_val)
 
     op1 = op1Mux(op1_sel)
     op2 = op2Mux(op2_sel)

regfile.py

@@ -4,6 +4,7 @@ from riscv_isa.isa import regNumToName
 class RegFile:
     def __init__(self):
         self.regs = [None]*32 #set all registers as none
+        self.regs[0] = 0
 
     def read(self, rs):
         return self.regs[rs] #read contents of register