Commit 701d1688 authored by Yu Christina Juan's avatar Yu Christina Juan
Browse files


parent a5ed2937
alu_ops = ['X','^','cp','sltu', 'and', 'add', 'slt', 'sra', 'sub', 'srl', 'sll', 'or']
def alu(op1,op2,alu_fun): # operation determined by the input alu_fun
if alu_fun == 0: # 0 (no operation)
return 0
if alu_fun == 1: #Xor
return op1^op2
if alu_fun == 2: #Copy (input 1 copied to output)
return op1
if alu_fun == 3: #Sltu (shift left unsigned)
return op1*(2**op2)
if alu_fun == 4: #And
return op1&op2
if alu_fun == 5: #Add
return op1+op2
if alu_fun == 6: #Slt (set less than)
return int(op1<op2)
if alu_fun == 7: #Sra (shift right arithmetic)
return op1>>op2
if alu_fun == 8: #Sub
return op1-op2
if alu_fun == 9: #Srl (shift right logical)
return (op1 % 0x100000000)>>op2
if alu_fun == 10: #Sll (shift left logical)
return (op1 % 0x100000000)<<op2
if alu_fun == 11: #Or
return op1|op2
#unit test
if __name__ == "__main__":
op1 = 0x100
op2 = 0x2
for i in range(12):
print(f"{op1:X}\t{alu_ops[i]}\t{op2:X} = {alu(op1, op2, i):X}")
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# filename:
def make_mux(*args): # Multiplexer that takes in variable # of args
return lambda i: args[i]()
# testbench
if __name__=="__main__":
mux = make_mux(lambda: 1,lambda: 2,lambda: 3,lambda: 4,lambda: 5)
for i in range(5):
print(f"mux({i}) == {mux(i)}")
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from riscv_isa.isa import regNumToName
class RegFile:
def __init__(self):
self.regs = [0]*32 #set all registers as 0
def read(self, rs):
return self.regs[rs] #read contents of register
def clock(self, wa, wd, en): #only write on negative edge
if wa <= 0 or wa >= 32 or wd == None or en == False:
if en == True:
self.regs[wa] = wd # write wd to wa
def display(self):
for i in range(0, 32, 4): # loop to display registers and their content
fmt_reg = lambda i: f"{self.regs[i]:09x}" if self.regs[i] != None else "xxxxxxxx"
print(" ".join([f"{regNumToName(i+j).rjust(4)}: {fmt_reg(i+j)}" for j in range(4)]))
if __name__=="__main__":
regFile = RegFile()
for i in range(32):
regFile.clock(i, 0x42 + i, True)
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