Commit edb3b3e2 authored by apaj's avatar apaj

Facing compatibility issues with examples Adder and Adder4, reverting those...

Facing compatibility issues with examples Adder and Adder4, reverting those two to original Chisel3 code until further notice
parent 7a77619e
*.original
*.inProgress
*.modComents
// See LICENSE.txt for license details.
// January 22nd, 2018 - Adapting to Learning Journey
package examples
import Chisel._
import chisel3._
//A n-bit adder with carry in and carry out
class Adder(n: Int) extends Module {
val io = new Bundle {
val A = UInt(INPUT, n)
val B = UInt(INPUT, n)
val Cin = UInt(INPUT, 1)
val Sum = UInt(OUTPUT, n)
val Cout = UInt(OUTPUT, 1)
}
// create a vector of FullAdders
val FAs = Vec.fill(n){ Module(new FullAdder()).io }
// define carry and sum wires
val carry = Vec.fill(n+1){ UInt(width = 1) }
val sum = Vec.fill(n){ Bool() }
// first carry is the top level carry in
carry(0) := io.Cin
// wire up the ports of the full adders
for(i <- 0 until n) {
FAs(i).a := io.A(i)
FAs(i).b := io.B(i)
FAs(i).cin := carry(i)
carry(i+1) := FAs(i).cout
sum(i) := FAs(i).sum.toBool()
}
io.Sum := sum.toBits().toUInt()
io.Cout := carry(n)
class Adder(val n:Int) extends Module {
val io = IO(new Bundle {
val A = Input(UInt(n.W))
val B = Input(UInt(n.W))
val Cin = Input(UInt(1.W))
val Sum = Output(UInt(n.W))
val Cout = Output(UInt(1.W))
})
//create an Array of FullAdders
// NOTE: Since we do all the wiring during elaboration and not at run-time,
// i.e., we don't need to dynamically index into the data structure at run-time,
// we use an Array instead of a Vec.
val FAs = Array.fill(n)(Module(new FullAdder()).io)
val carry = Wire(Vec(n+1, UInt(1.W)))
val sum = Wire(Vec(n, Bool()))
//first carry is the top level carry in
carry(0) := io.Cin
//wire up the ports of the full adders
for (i <- 0 until n) {
FAs(i).a := io.A(i)
FAs(i).b := io.B(i)
FAs(i).cin := carry(i)
carry(i+1) := FAs(i).cout
sum(i) := FAs(i).sum.toBool()
}
io.Sum := sum.asUInt
io.Cout := carry(n)
}
// See LICENSE.txt for license details.
// January 22nd, 2018 - adapting to Learning Journey
package examples
import Chisel._
import chisel3._
import chisel3.util._
//A 4-bit adder with carry in and carry out
class Adder4 extends Module {
val io = new Bundle {
val A = UInt(INPUT, 4)
val B = UInt(INPUT, 4)
val Cin = UInt(INPUT, 1)
val Sum = UInt(OUTPUT, 4)
val Cout = UInt(OUTPUT, 1)
}
val io = IO(new Bundle {
val A = Input(UInt(4.W))
val B = Input(UInt(4.W))
val Cin = Input(UInt(1.W))
val Sum = Output(UInt(4.W))
val Cout = Output(UInt(1.W))
})
//Adder for bit 0
val Adder0 = Module(new FullAdder())
Adder0.io.a := io.A(0)
......@@ -36,6 +36,6 @@ class Adder4 extends Module {
Adder3.io.a := io.A(3)
Adder3.io.b := io.B(3)
Adder3.io.cin := Adder2.io.cout
io.Sum := Cat(Adder3.io.sum, s2).toUInt()
io.Sum := Cat(Adder3.io.sum, s2).asUInt
io.Cout := Adder3.io.cout
}
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