Commit e412179d authored by apaj's avatar apaj
Browse files

Updated README, corrected Adder and Adder4 examples

parent edb3b3e2

.gitignore

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*.original

*.inProgress

*.modComents

*.commented

README.md

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@@ -20,7 +20,7 @@ then change the directory: 
cd learning-journey

```



and run the script that sets everythin up for you:

and run the script that sets everything up for you:



```

sudo ./set-learning-journey

src/main/scala/examples/Adder.scala

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// See LICENSE.txt for license details.

/ See LICENSE.txt for license details.

// January 23rd, 2018   - Adapting to Learning Journey

package examples



import chisel3._

import Chisel._



//A n-bit adder with carry in and carry out

class Adder(val n:Int) extends Module {

  val io = IO(new Bundle {

    val A    = Input(UInt(n.W))

    val B    = Input(UInt(n.W))

    val Cin  = Input(UInt(1.W))

    val Sum  = Output(UInt(n.W))

    val Cout = Output(UInt(1.W))

  })

  //create an Array of FullAdders

  //  NOTE: Since we do all the wiring during elaboration and not at run-time,

  //  i.e., we don't need to dynamically index into the data structure at run-time,

  //  we use an Array instead of a Vec.

  val FAs   = Array.fill(n)(Module(new FullAdder()).io)

  val carry = Wire(Vec(n+1, UInt(1.W)))

  val io = new Bundle {

    val A    = UInt(INPUT, n)

    val B    = UInt(INPUT, n)

    val Cin  = UInt(INPUT, 1)

    val Sum  = UInt(OUTPUT, n)

    val Cout = UInt(OUTPUT, 1)

  }

  //create a vector of FullAdders

  val FAs   = Vec(Seq.fill(n)(Module(new FullAdder()).io))

  val carry = Wire(Vec(n+1, UInt(width = 1)))

  val sum   = Wire(Vec(n, Bool()))



  //first carry is the top level carry in
@@ -31,6 +29,7 @@ class Adder(val n:Int) extends Module { 
    carry(i+1) := FAs(i).cout

    sum(i) := FAs(i).sum.toBool()

  }

  io.Sum := sum.asUInt

  io.Sum := sum.toBits.asUInt()

  io.Cout := carry(n)

}

src/main/scala/examples/Adder4.scala

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// See LICENSE.txt for license details.

// January 22nd, 2018   - adapting to Learning Journey

package examples



import chisel3._

import chisel3.util._

import Chisel._



//A 4-bit adder with carry in and carry out

class Adder4 extends Module {

  val io = IO(new Bundle {

    val A    = Input(UInt(4.W))

    val B    = Input(UInt(4.W))

    val Cin  = Input(UInt(1.W))

    val Sum  = Output(UInt(4.W))

    val Cout = Output(UInt(1.W))

  })

  val io = new Bundle {

    val A    = UInt(INPUT, 4)

    val B    = UInt(INPUT, 4)

    val Cin  = UInt(INPUT, 1)

    val Sum  = UInt(OUTPUT, 4)

    val Cout = UInt(OUTPUT, 1)

  }

  //Adder for bit 0

  val Adder0 = Module(new FullAdder())

  Adder0.io.a := io.A(0)
@@ -36,6 +36,6 @@ class Adder4 extends Module { 
  Adder3.io.a := io.A(3)

  Adder3.io.b := io.B(3)

  Adder3.io.cin := Adder2.io.cout

  io.Sum := Cat(Adder3.io.sum, s2).asUInt

  io.Sum := Cat(Adder3.io.sum, s2).asUInt()

  io.Cout := Adder3.io.cout

}