Commit af488ad7 authored by apaj's avatar apaj

Correcting typos in Adder and VecShiftRegisterSimple problems

parent 317ace0c
......@@ -16,6 +16,6 @@ class Adder(val w: Int) extends Module {
val in1 = UInt(INPUT, 1)
val out = UInt(OUTPUT, 1)
}
...
// ...
io.out := UInt(0)
}
......@@ -15,6 +15,6 @@ class VecShiftRegisterSimple extends Module {
val out = UInt(OUTPUT, 8)
}
val delays = Vec.fill(4){ Reg(UInt(width = 8)) }
...
// ...
io.out := UInt(0)
}
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