Commit af488ad7 authored Jan 23, 2018 by apaj

Correcting typos in Adder and VecShiftRegisterSimple problems

parent 317ace0c

src/main/scala/problems/Adder.scala

+1 −1

Original line number	Diff line number	Diff line
		@@ -16,6 +16,6 @@ class Adder(val w: Int) extends Module {
		val in1 = UInt(INPUT, 1)
		val out = UInt(OUTPUT, 1)
		}
		...
		// ...
		io.out := UInt(0)
		}

src/main/scala/problems/VecShiftRegisterSimple.scala

+1 −1

Original line number	Diff line number	Diff line
		@@ -15,6 +15,6 @@ class VecShiftRegisterSimple extends Module {
		val out = UInt(OUTPUT, 8)
		}
		val delays = Vec.fill(4){ Reg(UInt(width = 8)) }
		...
		// ...
		io.out := UInt(0)
		}