Adapted Accumulator problem/solution

// See LICENSE.txt for license details.

// January 20th, 2018	-adapted for Learning Journey

package problems

import chisel3._

import Chisel._

// Problem:

//

// (increase counter every clock if 'in' is asserted)

//

class Accumulator extends Module { 

  val io = IO(new Bundle {

    val in  = Input(UInt(1.W))

    val out = Output(UInt(8.W))

  })

  // Implement below ----------

  val io = new Bundle { 

    val in  = UInt(INPUT, 1) 

    val out = UInt(OUTPUT, 8) 

  } 

  io.out := 0.U

  // flush this out ... 

  // Implement above ----------

  io.out := UInt(0) 

}

// See LICENSE.txt for license details.

// January 20th, 2018	- adapted for Learning Journey

package solutions

import chisel3._

import Chisel._

// Problem:

//

// Count incoming trues

// (increase counter every clock if 'in' is asserted)

//

class Accumulator extends Module {

  val io = IO(new Bundle {

    val in  = Input(UInt(1.W))

    val out = Output(UInt(8.W))

  })

  val accumulator = RegInit(0.U(8.W))

  val io = new Bundle {

    val in  = UInt(width = 1, dir = INPUT)

    val out = UInt(width = 8, dir = OUTPUT)

  }

  val accumulator = Reg(init=UInt(0, 8))

  accumulator := accumulator + io.in

  io.out := accumulator

}