Commit 7a77619e authored by apaj's avatar apaj

To correctly run LFSR16 solution, removed line importing . Adapting Adder and...

To correctly run LFSR16 solution, removed line importing . Adapting Adder and Adder4 examples; Adder and VecshiftRegisterSimple problems and solutions
parent 744fa133
// See LICENSE.txt for license details.
// January 22nd, 2018 - Adapting to Learning Journey
package examples
import chisel3._
import Chisel._
//A n-bit adder with carry in and carry out
class Adder(val n:Int) extends Module {
val io = IO(new Bundle {
val A = Input(UInt(n.W))
val B = Input(UInt(n.W))
val Cin = Input(UInt(1.W))
val Sum = Output(UInt(n.W))
val Cout = Output(UInt(1.W))
})
//create an Array of FullAdders
// NOTE: Since we do all the wiring during elaboration and not at run-time,
// i.e., we don't need to dynamically index into the data structure at run-time,
// we use an Array instead of a Vec.
val FAs = Array.fill(n)(Module(new FullAdder()).io)
val carry = Wire(Vec(n+1, UInt(1.W)))
val sum = Wire(Vec(n, Bool()))
//first carry is the top level carry in
carry(0) := io.Cin
//wire up the ports of the full adders
for (i <- 0 until n) {
FAs(i).a := io.A(i)
FAs(i).b := io.B(i)
FAs(i).cin := carry(i)
carry(i+1) := FAs(i).cout
sum(i) := FAs(i).sum.toBool()
}
io.Sum := sum.asUInt
io.Cout := carry(n)
class Adder(n: Int) extends Module {
val io = new Bundle {
val A = UInt(INPUT, n)
val B = UInt(INPUT, n)
val Cin = UInt(INPUT, 1)
val Sum = UInt(OUTPUT, n)
val Cout = UInt(OUTPUT, 1)
}
// create a vector of FullAdders
val FAs = Vec.fill(n){ Module(new FullAdder()).io }
// define carry and sum wires
val carry = Vec.fill(n+1){ UInt(width = 1) }
val sum = Vec.fill(n){ Bool() }
// first carry is the top level carry in
carry(0) := io.Cin
// wire up the ports of the full adders
for(i <- 0 until n) {
FAs(i).a := io.A(i)
FAs(i).b := io.B(i)
FAs(i).cin := carry(i)
carry(i+1) := FAs(i).cout
sum(i) := FAs(i).sum.toBool()
}
io.Sum := sum.toBits().toUInt()
io.Cout := carry(n)
}
// See LICENSE.txt for license details.
// January 22nd, 2018 - adapting to Learning Journey
package examples
import chisel3._
import chisel3.util._
import Chisel._
//A 4-bit adder with carry in and carry out
class Adder4 extends Module {
val io = IO(new Bundle {
val A = Input(UInt(4.W))
val B = Input(UInt(4.W))
val Cin = Input(UInt(1.W))
val Sum = Output(UInt(4.W))
val Cout = Output(UInt(1.W))
})
val io = new Bundle {
val A = UInt(INPUT, 4)
val B = UInt(INPUT, 4)
val Cin = UInt(INPUT, 1)
val Sum = UInt(OUTPUT, 4)
val Cout = UInt(OUTPUT, 1)
}
//Adder for bit 0
val Adder0 = Module(new FullAdder())
Adder0.io.a := io.A(0)
......@@ -36,6 +36,6 @@ class Adder4 extends Module {
Adder3.io.a := io.A(3)
Adder3.io.b := io.B(3)
Adder3.io.cin := Adder2.io.cout
io.Sum := Cat(Adder3.io.sum, s2).asUInt
io.Sum := Cat(Adder3.io.sum, s2).toUInt()
io.Cout := Adder3.io.cout
}
// See LICENSE.txt for license details.
// January 22nd, 2018 - Adapted to Learning Journey
package problems
import chisel3._
import Chisel._
// Problem:
//
......@@ -9,13 +10,12 @@ import chisel3._
// Adder width should be parametrized
//
// Implement below ----------
class Adder(val w: Int) extends Module {
val io = IO(new Bundle {
val in0 = Input(UInt(1.W))
val in1 = Input(UInt(1.W))
val out = Output(UInt(1.W))
})
io.out := 0.U
class Adder(val w: Int) extends Module {
val io = new Bundle {
val in0 = UInt(INPUT, 1)
val in1 = UInt(INPUT, 1)
val out = UInt(OUTPUT, 1)
}
...
io.out := UInt(0)
}
// Implement above ----------
// See LICENSE.txt for license details.
// January 22nd, 2018 - adapting to Learnin Journey
package problems
import chisel3._
import Chisel._
// Problem:
//
// Implement a shift register with four 8-bit stages.
// Shift should occur on every clock.
//
class VecShiftRegisterSimple extends Module {
val io = IO(new Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
})
val initValues = Seq.fill(4) { 0.U(8.W) }
val delays = RegInit(Vec(initValues))
// Implement below ----------
io.out := 0.U
// Implement above ----------
class VecShiftRegisterSimple extends Module {
val io = new Bundle {
val in = UInt(INPUT, 8)
val out = UInt(OUTPUT, 8)
}
val delays = Vec.fill(4){ Reg(UInt(width = 8)) }
...
io.out := UInt(0)
}
// See LICENSE.txt for license details.
// January 22nd, 2018 - Adapted to Learning Joruney
package solutions
import chisel3._
import Chisel._
// Problem:
//
......@@ -9,10 +10,10 @@ import chisel3._
// Adder width should be parametrized
//
class Adder(val w: Int) extends Module {
val io = IO(new Bundle {
val in0 = Input(UInt(w.W))
val in1 = Input(UInt(w.W))
val out = Output(UInt(w.W))
})
val io = new Bundle {
val in0 = UInt(INPUT, w)
val in1 = UInt(INPUT, w)
val out = UInt(OUTPUT, w)
}
io.out := io.in0 + io.in1
}
......@@ -3,7 +3,6 @@
package solutions
import Chisel._
import Chisel.util.Cat
// Problem:
//
......
// See LICENSE.txt for license details.
// January 22nd, 2018 - adapting to Learning Journey
package solutions
import chisel3._
import Chisel._
// Problem:
//
......@@ -9,14 +10,11 @@ import chisel3._
// Shift should occur on every clock.
//
class VecShiftRegisterSimple extends Module {
val io = IO(new Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
})
val initValues = Seq.fill(4) { 0.U(8.W) }
val delays = RegInit(Vec(initValues))
val io = new Bundle {
val in = UInt(INPUT, 8)
val out = UInt(OUTPUT, 8)
}
val delays = Reg(init = Vec(4, UInt(0, width = 8)))
delays(0) := io.in
delays(1) := delays(0)
delays(2) := delays(1)
......
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