Commit 71c86679 authored by apaj's avatar apaj
Browse files

Testing LFSR solution

parent 83673875
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+8 −8
Original line number Diff line number Diff line
// See LICENSE.txt for license details.
// January 21st, 2018	- adapting for Learning Journey
package solutions

import chisel3._
import chisel3.util.Cat
import Chisel._
import Chisel.util.Cat

// Problem:
//
@@ -11,12 +12,11 @@ import chisel3.util.Cat
// State change is allowed only when 'inc' is asserted
//
class LFSR16 extends Module {
  val io = IO(new Bundle {
    val inc = Input(Bool())
    val out = Output(UInt(16.W))
  })

  val res = RegInit(1.U(16.W))
  val io = new Bundle {
    val inc = Bool(INPUT)
    val out = UInt(OUTPUT, 16)
  }
  val res = Reg(init = UInt(1, 16))
  when (io.inc) { 
    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
    res := nxt_res