As agreed, switching back to Chisel3

.gitignore

@@ -2,3 +2,5 @@
 *.inProgress
 *.modComents
 *.commented
+*.chisel2
+rename.sh

README.md

@@ -6,8 +6,6 @@ Welcome to the Chisel Learning Journey!
 
 This Journey is built around the examples provided by the creators of Chisel, within their [tutorial](https://github.com/ucb-bar/chisel-tutorial).
 
-However, ...
-
 Please clone the Learning Journey:
 
 ```

src/main/scala/examples/Adder.scala

 // See LICENSE.txt for license details.
-// January 23rd, 2018   - Adapting to Learning Journey
 package examples
 
-import Chisel._
-import chisel3.core.VecInit
+import chisel3._
 
 //A n-bit adder with carry in and carry out
 class Adder(val n:Int) extends Module {
-  val io = new Bundle {
-    val A    = UInt(INPUT, n)
-    val B    = UInt(INPUT, n)
-    val Cin  = UInt(INPUT, 1)
-    val Sum  = UInt(OUTPUT, n)
-    val Cout = UInt(OUTPUT, 1)
-  }
-  //create a vector of FullAdders
-  val FAs   = VecInit(Seq.fill(n)(Module(new FullAdder()).io))
-  val carry = Wire(Vec(n+1, UInt(width = 1)))
+  val io = IO(new Bundle {
+    val A    = Input(UInt(n.W))
+    val B    = Input(UInt(n.W))
+    val Cin  = Input(UInt(1.W))
+    val Sum  = Output(UInt(n.W))
+    val Cout = Output(UInt(1.W))
+  })
+  //create an Array of FullAdders
+  //  NOTE: Since we do all the wiring during elaboration and not at run-time,
+  //  i.e., we don't need to dynamically index into the data structure at run-time,
+  //  we use an Array instead of a Vec.
+  val FAs   = Array.fill(n)(Module(new FullAdder()).io)
+  val carry = Wire(Vec(n+1, UInt(1.W)))
   val sum   = Wire(Vec(n, Bool()))
 
   //first carry is the top level carry in
@@ -30,7 +31,6 @@ class Adder(val n:Int) extends Module {
     carry(i+1) := FAs(i).cout
     sum(i) := FAs(i).sum.toBool()
   }
-  io.Sum := sum.asUInt()
+  io.Sum := sum.asUInt
   io.Cout := carry(n)
 }
-

src/main/scala/examples/Adder4.scala

 // See LICENSE.txt for license details.
-// January 22nd, 2018   - adapting to Learning Journey
 package examples
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 
 //A 4-bit adder with carry in and carry out
 class Adder4 extends Module {
-  val io = new Bundle {
-    val A    = UInt(INPUT, 4)
-    val B    = UInt(INPUT, 4)
-    val Cin  = UInt(INPUT, 1)
-    val Sum  = UInt(OUTPUT, 4)
-    val Cout = UInt(OUTPUT, 1)
-  }
+  val io = IO(new Bundle {
+    val A    = Input(UInt(4.W))
+    val B    = Input(UInt(4.W))
+    val Cin  = Input(UInt(1.W))
+    val Sum  = Output(UInt(4.W))
+    val Cout = Output(UInt(1.W))
+  })
   //Adder for bit 0
   val Adder0 = Module(new FullAdder())
   Adder0.io.a := io.A(0)
@@ -36,6 +36,6 @@ class Adder4 extends Module {
   Adder3.io.a := io.A(3)
   Adder3.io.b := io.B(3)
   Adder3.io.cin := Adder2.io.cout
-  io.Sum := Cat(Adder3.io.sum, s2).asUInt()
+  io.Sum := Cat(Adder3.io.sum, s2).asUInt
   io.Cout := Adder3.io.cout
-} 
+}

src/main/scala/examples/ByteSelector.scala

 // See LICENSE.txt for license details.
-// January 21st, 2018	- adapting to Learning Journey
-
 package examples
 
-import Chisel._
+import chisel3._
 
-class ByteSelector extends Module { 
-  val io = new Bundle { 
-    val in     = UInt(INPUT, 32) 
-    val offset = UInt(INPUT, 2) 
-    val out    = UInt(OUTPUT, 8) 
-  } 
-  io.out := UInt(0, width = 8) 
-  when (io.offset === UInt(0)) { 
-    io.out := io.in(7,0) // pull out lowest byte 
-  } .elsewhen (io.offset === UInt(1)) { 
-    io.out := io.in(15,8) // pull out second byte 
-  } .elsewhen (io.offset === UInt(2)) { 
-    io.out := io.in(23,16) // pull out third byte 
-  } .otherwise { 
-    io.out := io.in(31,24) // pull out highest byte 
-  } 
+class ByteSelector extends Module {
+  val io = IO(new Bundle {
+    val in     = Input(UInt(32.W))
+    val offset = Input(UInt(2.W))
+    val out    = Output(UInt(8.W))
+  })
+  io.out := 0.U(8.W)
+  when (io.offset === 0.U(2.W)) {
+    io.out := io.in(7,0)
+  } .elsewhen (io.offset === 1.U) {
+    io.out := io.in(15,8)
+  } .elsewhen (io.offset === 2.U) {
+    io.out := io.in(23,16)
+  } .otherwise {
+    io.out := io.in(31,24)
+  }
 }

src/main/scala/examples/FullAdder.scala

 // See LICENSE.txt for license details.
-// January 20th, 2018	-adapted to Learning Journey
-
 package examples
 
-import Chisel._
+import chisel3._
+
+class FullAdder extends Module {
+  val io = IO(new Bundle {
+    val a    = Input(UInt(1.W))
+    val b    = Input(UInt(1.W))
+    val cin  = Input(UInt(1.W))
+    val sum  = Output(UInt(1.W))
+    val cout = Output(UInt(1.W))
+  })
 
-class FullAdder extends Module { 
-  val io = new Bundle { 
-    val a    = UInt(INPUT, 1) 
-    val b    = UInt(INPUT, 1) 
-    val cin  = UInt(INPUT, 1) 
-    val sum  = UInt(OUTPUT, 1) 
-    val cout = UInt(OUTPUT, 1) 
-  } 
-  // Generate the sum 
-  val a_xor_b = io.a ^ io.b 
-  io.sum := a_xor_b ^ io.cin 
-  // Generate the carry 
-  val a_and_b = io.a & io.b 
-  val b_and_cin = io.b & io.cin 
-  val a_and_cin = io.a & io.cin 
-  io.cout := a_and_b | b_and_cin | a_and_cin 
+  // Generate the sum
+  val a_xor_b = io.a ^ io.b
+  io.sum := a_xor_b ^ io.cin
+  // Generate the carry
+  val a_and_b = io.a & io.b
+  val b_and_cin = io.b & io.cin
+  val a_and_cin = io.a & io.cin
+  io.cout := a_and_b | b_and_cin | a_and_cin
 }

src/main/scala/examples/GCD.scala

 // See LICENSE.txt for license details.
-// January 20th, 2018	- adapted to Learning Journey
 package examples
 
-import Chisel._ 
- 
-class GCD extends Module { 
-  val io = new Bundle { 
-    val a  = UInt(INPUT,  16) 
-    val b  = UInt(INPUT,  16) 
-    val e  = Bool(INPUT) 
-    val z  = UInt(OUTPUT, 16) 
-    val v  = Bool(OUTPUT) 
-  } 
-  val x  = Reg(UInt()) 
-  val y  = Reg(UInt()) 
-  when   (x > y) { x := x - y } 
-  unless (x > y) { y := y - x } 
-  when (io.e) { x := io.a; y := io.b } 
-  io.z := x 
-  io.v := y === UInt(0) 
-}
+import chisel3._
+
+class GCD extends Module {
+  val io = IO(new Bundle {
+    val a  = Input(UInt(16.W))
+    val b  = Input(UInt(16.W))
+    val e  = Input(Bool())
+    val z  = Output(UInt(16.W))
+    val v  = Output(Bool())
+  })
+
+  val x  = Reg(UInt())
+  val y  = Reg(UInt())
+  when   (x > y) {
+    x := x - y
+  }
+    .elsewhen (x <= y) { y := y - x }
+
+  when (io.e) { x := io.a; y := io.b }
+  io.z := x
+  io.v := y === 0.U
+}
\ No newline at end of file

src/main/scala/examples/HiLoMultiplier.scala

 // See LICENSE.txt for license details.
-// January 22nd, 2018	- adapted to Learning Journey
-
 package examples
 
-import Chisel._
+import chisel3._
 
 //A 4-bit adder with carry in and carry out
-class HiLoMultiplier() extends Module { 
-  val io = new Bundle { 
-    val A  = UInt(INPUT, 16) 
-    val B  = UInt(INPUT, 16) 
-    val Hi = UInt(OUTPUT, 16) 
-    val Lo = UInt(OUTPUT, 16) 
-  } 
-  val mult = io.A * io.B 
-  io.Lo := mult(15, 0) 
-  io.Hi := mult(31, 16) 
+class HiLoMultiplier() extends Module {
+  val io = IO(new Bundle {
+    val A  = Input(UInt(16.W))
+    val B  = Input(UInt(16.W))
+    val Hi = Output(UInt(16.W))
+    val Lo = Output(UInt(16.W))
+  })
+  val mult = io.A * io.B
+  io.Lo := mult(15, 0)
+  io.Hi := mult(31, 16)
 }

src/main/scala/examples/ShiftRegister.scala

 // See LICENSE.txt for license details.
 package examples
 
-import Chisel._
+import chisel3._
 
-class ShiftRegister extends Module { 
-  val io = new Bundle { 
-    val in  = UInt(INPUT, 1) 
-    val out = UInt(OUTPUT, 1) 
-  } 
-  val r0 = Reg(next = io.in) 
-  val r1 = Reg(next = r0) 
-  val r2 = Reg(next = r1) 
-  val r3 = Reg(next = r2) 
-  io.out := r3 
+class ShiftRegister extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
+  })
+  val r0 = RegNext(io.in)
+  val r1 = RegNext(r0)
+  val r2 = RegNext(r1)
+  val r3 = RegNext(r2)
+  io.out := r3
 }

src/main/scala/examples/SimpleALU.scala

 // See LICENSE.txt for license details.
-// January 21st, 2018	- adapting BasicALU to Learning Journey
 package examples
 
-import Chisel._
+import chisel3._
 
-class BasicALU extends Module { 
-  val io = new Bundle { 
-    val a      = UInt(INPUT, 4) 
-    val b      = UInt(INPUT, 4) 
-    val opcode = UInt(INPUT, 4) 
-    val output = UInt(OUTPUT, 4) 
-  } 
-  io.output := UInt(0) 
-  when (io.opcode === UInt(0)) { 
-    io.output := io.a                   // pass A 
-  } .elsewhen (io.opcode === UInt(1)) { 
-    io.output := io.b                   // pass B 
-  } .elsewhen (io.opcode === UInt(2)) { 
-    io.output := io.a + UInt(1)         // inc A by 1 
-  } .elsewhen (io.opcode === UInt(3)) { 
-    io.output := io.a - UInt(1)         // inc B by 1 
-  } .elsewhen (io.opcode === UInt(4)) { 
-    io.output := io.a + UInt(4)         // inc A by 4 
-  } .elsewhen (io.opcode === UInt(5)) { 
-    io.output := io.a - UInt(4)         // dec A by 4 
-  } .elsewhen (io.opcode === UInt(6)) { 
-    io.output := io.a + io.b            // add A and B 
-  } .elsewhen (io.opcode === UInt(7)) { 
-    io.output := io.a - io.b            // sub B from A 
-  } .elsewhen (io.opcode === UInt(8)) { 
-    io.output := (io.a < io.b)          // set on A < B 
+class BasicALU extends Module {
+  val io = IO(new Bundle {
+    val a = Input(UInt(4.W))
+    val b = Input(UInt(4.W))
+    val opcode = Input(UInt(4.W))
+    val out = Output(UInt(4.W))
+  })
+  io.out := 0.U //THIS SEEMS LIKE A HACK/BUG
+  when (io.opcode === 0.U) {
+    io.out := io.a //pass A
+  } .elsewhen (io.opcode === 1.U) {
+    io.out := io.b //pass B
+  } .elsewhen (io.opcode === 2.U) {
+    io.out := io.a + 1.U //increment A by 1
+  } .elsewhen (io.opcode === 3.U) {
+    io.out := io.a - 1.U //increment B by 1
+  } .elsewhen (io.opcode === 4.U) {
+    io.out := io.a + 4.U //increment A by 4
+  } .elsewhen (io.opcode === 5.U) {
+    io.out := io.a - 4.U //decrement A by 4
+  } .elsewhen (io.opcode === 6.U) {
+    io.out := io.a + io.b //add A and B
+  } .elsewhen (io.opcode === 7.U) {
+    io.out := io.a - io.b //subtract B from A
+  } .elsewhen (io.opcode === 8.U) {
+    io.out := io.a < io.b //set on A less than B
   } .otherwise { 
-    io.output := (io.a === io.b)        // set on A == B 
-  } 
+    io.out :=  (io.a === io.b).asUInt //set on A equal to B
+  }
 }
 
 class SimpleALU extends Module {
-  val io = new Bundle {
-    val a      = UInt(INPUT,  4)
-    val b      = UInt(INPUT,  4)
-    val opcode = UInt(INPUT,  2)
-    val out = UInt(OUTPUT, 4)
-  }
-  io.out := UInt(0) 
-  when (io.opcode === UInt(0)) {
+  val io = IO(new Bundle {
+    val a      = Input(UInt(4.W))
+    val b      = Input(UInt(4.W))
+    val opcode = Input(UInt(2.W))
+    val out = Output(UInt(4.W))
+  })
+  io.out := 0.U
+  when (io.opcode === 0.U) {
     io.out := io.a + io.b //ADD
-  } .elsewhen (io.opcode === UInt(1)) {
+  } .elsewhen (io.opcode === 1.U) {
     io.out := io.a - io.b //SUB
-  } .elsewhen (io.opcode === UInt(2)) {
+  } .elsewhen (io.opcode === 2.U) {
     io.out := io.a  	     //PASS A
   } .otherwise {
     io.out := io.b        //PASS B

src/main/scala/problems/Accumulator.scala

 // See LICENSE.txt for license details.
-// January 20th, 2018	-adapted for Learning Journey
 package problems
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
 // Count incoming trues
 // (increase counter every clock if 'in' is asserted)
 //
-class Accumulator extends Module { 
-  val io = new Bundle { 
-    val in  = UInt(INPUT, 1) 
-    val out = UInt(OUTPUT, 8) 
-  } 
- 
-  // flush this out ... 
- 
-  io.out := UInt(0) 
+class Accumulator extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(1.W))
+    val out = Output(UInt(8.W))
+  })
+
+  // Implement below ----------
+
+  io.out := 0.U
+
+  // Implement above ----------
 }

src/main/scala/problems/LFSR16.scala

 // See LICENSE.txt for license details.
-// January 21st, 2018	- adapting to Learning Journey
 package problems
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
@@ -10,11 +9,15 @@ import Chisel._
 // with polynomial x^16 + x^14 + x^13 + x^11 + 1
 // State change is allowed only when 'inc' is asserted
 //
-class LFSR16 extends Module { 
-  val io = new Bundle { 
-    val inc = Bool(INPUT) 
-    val out = UInt(OUTPUT, 16) 
-  } 
-  // ... 
-  io.out := UInt(0) 
+class LFSR16 extends Module {
+  val io = IO(new Bundle {
+    val inc = Input(Bool())
+    val out = Output(UInt(16.W))
+  })
+
+  // Implement below ----------
+
+  io.out := 0.U
+
+  // Implement above ----------
 }

src/main/scala/problems/VecShiftRegisterSimple.scala

 // See LICENSE.txt for license details.
-// January 22nd, 2018	- adapting to Learnin Journey
 package problems
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
 // Implement a shift register with four 8-bit stages.
 // Shift should occur on every clock.
 //
-class VecShiftRegisterSimple extends Module { 
-  val io = new Bundle { 
-    val in  = UInt(INPUT,  8) 
-    val out = UInt(OUTPUT, 8) 
-  } 
-  val delays = Vec.fill(4){ Reg(UInt(width = 8)) } 
-//  ... 
-  io.out := UInt(0) 
+class VecShiftRegisterSimple extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+
+  val initValues = Seq.fill(4) { 0.U(8.W) }
+  val delays = RegInit(Vec(initValues))
+
+  // Implement below ----------
+
+  io.out := 0.U
+
+  // Implement above ----------
 }

src/main/scala/solutions/Accumulator.scala

 // See LICENSE.txt for license details.
-// January 20th, 2018	- adapted for Learning Journey
 package solutions
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
 // Count incoming trues
 // (increase counter every clock if 'in' is asserted)
+//
 class Accumulator extends Module {
-  val io = new Bundle {
-    val in  = UInt(width = 1, dir = INPUT)
-    val out = UInt(width = 8, dir = OUTPUT)
-  }
-  val accumulator = Reg(init=UInt(0, 8))
+  val io = IO(new Bundle {
+    val in  = Input(UInt(1.W))
+    val out = Output(UInt(8.W))
+  })
+  val accumulator = RegInit(0.U(8.W))
   accumulator := accumulator + io.in
   io.out := accumulator
 }

src/main/scala/solutions/Adder.scala

 // See LICENSE.txt for license details.
-// January 22nd, 2018	- Adapted to Learning Joruney
 package solutions
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
@@ -10,10 +9,10 @@ import Chisel._
 // Adder width should be parametrized
 //
 class Adder(val w: Int) extends Module {
-  val io = new Bundle {
-    val in0 = UInt(INPUT,  w)
-    val in1 = UInt(INPUT,  w)
-    val out = UInt(OUTPUT, w)
-  }
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(w.W))
+    val in1 = Input(UInt(w.W))
+    val out = Output(UInt(w.W))
+  })
   io.out := io.in0 + io.in1
 }

src/main/scala/solutions/LFSR16.scala

 // See LICENSE.txt for license details.
-// January 21st, 2018	- adapting for Learning Journey
 package solutions
 
-import Chisel._
+import chisel3._
+import chisel3.util.Cat
 
 // Problem:
 //
@@ -11,11 +11,12 @@ import Chisel._
 // State change is allowed only when 'inc' is asserted
 //
 class LFSR16 extends Module {
-  val io = new Bundle {
-    val inc = Bool(INPUT)
-    val out = UInt(OUTPUT, 16)
-  }
-  val res = Reg(init = UInt(1, 16))
+  val io = IO(new Bundle {
+    val inc = Input(Bool())
+    val out = Output(UInt(16.W))
+  })
+
+  val res = RegInit(1.U(16.W))
   when (io.inc) { 
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
     res := nxt_res

src/main/scala/solutions/VecShiftRegisterSimple.scala

 // See LICENSE.txt for license details.
-// January 22nd, 2018	- adapting to Learning Journey
 package solutions
 
-import Chisel._
+import chisel3._
 
 // Problem:
 //
@@ -10,11 +9,14 @@ import Chisel._
 // Shift should occur on every clock.
 //
 class VecShiftRegisterSimple extends Module {
-  val io = new Bundle {
-    val in  = UInt(INPUT,  8)
-    val out = UInt(OUTPUT, 8)
-  }
-  val delays = Reg(init = Vec(4, UInt(0, width = 8)))
+  val io = IO(new Bundle {
+    val in  = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+
+  val initValues = Seq.fill(4) { 0.U(8.W) }
+  val delays = RegInit(Vec(initValues))
+
   delays(0) := io.in
   delays(1) := delays(0)
   delays(2) := delays(1)